As the density of semiconductor devices increases, the demands on interconnect layers for connecting the semiconductor devices to each other also increases. Therefore, there is a desire to switch from the traditional aluminum metal interconnects to copper interconnects. Unfortunately, suitable copper etches for a semiconductor fabrication environment are not readily available. To overcome the copper etch problem, damascene processes have been developed.
In a damascene process, the IMD is formed first. The IMD is then patterned and etched to form a trench for the interconnect line. If connection vias have not already been formed, a dual damascene process may be used. In a dual damascene process, after the trench is formed in the IMD, a via is etched in the ILD for connection to lower interconnect levels. The barrier layer 14 and a copper seed layer are then deposited over the structure. The barrier layer 14 is typically tantalum nitride or some other binary transition metal nitride. The copper layer is the formed using the seed layer over the entire structure. The copper is then chemically-mechanically polished (CMP'd) to remove the copper from over the IMD 16, leaving copper interconnect lines 18 and vias 20 as shown in FIG. 1. A metal etch is thereby avoided.
Further improvements in interconnect performance are desired. Accordingly, efforts are being made to include low-k dielectric materials in a copper interconnect structure.